Communication Protocols — question 10 of 10
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You have an I2C sensor that occasionally needs extra time to prepare a byte, so it holds SCL low (clock stretching) for up to 5ms during a read. Your master implementation has a bus timeout of 2ms: if it doesn't see the expected SCL/SDA states within that window, it aborts the transaction and resets its I2C peripheral. In testing, most reads succeed, but a small fraction fail -- and worse, occasionally the whole bus locks up afterward, requiring a power cycle to recover. Walk me through the failure chain here, and how you'd fix it robustly.