Computer Architecture — question 10 of 10
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Assume the DMA engine has no visibility into the CPU's cache contents and there is no hardware cache-coherence protocol between them.
A system has a CPU with a write-back data cache and a DMA engine that reads sensor data and writes it directly into main memory, bypassing the CPU's cache entirely. After a DMA transfer completes and the CPU is signaled to read the new data, it sometimes reads stale values instead of what the DMA just wrote. Walk me through the mechanism causing this, and describe at least two different ways a system could actually fix it.