Computer Architecture — question 5 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
Assume no forwarding issues are involved -- data hazards have already been ruled out by inspecting the register dependencies.
You're looking at a simple 5-stage scalar pipeline (IF, ID, EX, MEM, WB) that has only a single unified memory with one port, shared by instruction fetch and data loads/stores -- there's no separate instruction cache. You notice extra one-cycle stalls happening that aren't explained by any data hazard between instructions. Digging into the trace, the stalls always occur when a load or store instruction is in its MEM stage at the same cycle another instruction is trying to do IF. What's going on, and how would a real design typically resolve it?