Computer Architecture — question 8 of 10
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Assume the bus can sustain its peak transfer rate every cycle with no protocol overhead, to keep the arithmetic focused on the core bandwidth budgeting question.
A shared on-chip bus runs at 200 MHz and transfers 8 bytes (64 bits) per cycle when fully utilized. Three agents need simultaneous access: a display controller needs a sustained 1500 MB/s to avoid frame underrun, a DMA engine averages 800 MB/s, and the CPU needs about 400 MB/s on average for cache refills. What percentage of the bus's peak bandwidth would be required to satisfy all three simultaneously, and what does that tell you about whether this bus can support the workload as-is?
This one resolves to a number. Give the value in the field below and your reasoning in the box — the number is checked exactly, by arithmetic.