Computer Architecture — question 9 of 10
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You're designing the memory hierarchy for a small embedded processor and have a fixed silicon area budget. You must choose between (a) a larger, more associative single-level cache, or (b) a smaller L1 backed by a modest L2, given that the target workload has a large but only moderately reused working set with occasional bursts of sequential access. Walk me through how you'd decide, including what you'd actually measure to justify the choice.