Digital Logic — question 10 of 10
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Each bit's 2-flop synchronizer is correctly designed and, in isolation, resolves metastability for that bit reliably.
A design passes a 4-bit binary counter value from clock domain A to clock domain B by giving each of the 4 bits its own independent 2-flop synchronizer in domain B. On the bench, you occasionally see domain B briefly read counter values that never actually occurred in domain A -- for example, seeing a 4 followed by an 11 when the counter was slowly incrementing by 1 each time. Explain why per-bit synchronization isn't sufficient here even though each individual bit is properly synchronized, and describe a technique that would fix it.