Digital Logic — question 3 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
Tests whether a candidate understands the difference between a state machine on paper and one that is actually implementable in real hardware with a clock.
You're asked to design a state machine that controls a single LED beacon: press a button once and it blinks slowly, press it again and it blinks fast, press it a third time and it turns off, then repeats. A junior teammate draws a state diagram with three states and, in the 'slow blink' state, has a combinational path that directly asserts the 'turn off' output based on both the current LED phase and the button signal, without going through a clocked register. Why is this implementation likely to be broken, and how would you fix it?