Digital Logic — question 5 of 10
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You're using a discrete chip from a datasheet and a function generator for the clock, probing D, clock, and Q with a scope.
You wired up what you believe is a D flip-flop clocked by a signal, and you expect the output Q to change only on the rising edge of the clock. During testing, you notice Q actually follows D and changes any time D changes while the clock is high, not just at the edge. What's most likely going on, and how would you prove it on the bench?