Digital Logic — question 6 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
This is the core timing-closure calculation every digital logic intern should be able to do without a tool, since it underlies why 'it works on the bench but not at full speed' failures happen.
A synchronous design has a flip-flop with clock-to-Q delay of 0.5 ns feeding a combinational block with worst-case propagation delay of 3.2 ns, which then feeds the data input of a second flip-flop with a setup time requirement of 0.4 ns. Board-level clock skew between the two flip-flops adds 0.3 ns of pessimism to the timing path. Ignoring hold time for this question, what is the maximum clock frequency this path can support?
This one resolves to a number. Give the value in the field below and your reasoning in the box — the number is checked exactly, by arithmetic.