Digital Logic — question 7 of 10
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Multi-bit clock domain crossing failures are one of the most common real bugs interns encounter once they move past single-bit synchronizer theory.
You have a free-running counter in clock domain A whose value is read directly (all bits, no synchronizer) by logic in clock domain B, which runs at an unrelated, asynchronous frequency. Occasionally, domain B reads a counter value that never actually existed in domain A -- not just a value that's one count behind, but a value that's numerically nonsensical given the counter's sequence. Explain what's happening and how you'd fix it.