Embedded Systems — question 3 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
This checks whether the candidate can translate a cycle budget into a real time figure, a routine task when validating real-time deadlines.
Your MCU runs at 48 MHz. On an interrupt request, the core needs 12 clock cycles to push context onto the stack, the interrupt controller adds 6 cycles of arbitration overhead when multiple sources are pending, and the vector fetch from flash takes 2 wait-state cycles. What is the minimum interrupt latency, in microseconds, from the interrupt assertion to the first instruction of the ISR executing?
This one resolves to a number. Give the value in the field below and your reasoning in the box — the number is checked exactly, by arithmetic.