FPGA & HDL — question 1 of 10
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The block looks like: always @(posedge clk) begin q[0] = d; q[1] = q[0]; q[2] = q[1]; ... q[7] = q[6]; end
You write an always block in Verilog to build an 8-bit shift register using blocking assignments (=) instead of non-blocking assignments (<=) for all the internal stage transfers. In simulation the output looks wrong -- it behaves like a single flip-flop instead of an 8-stage shift register. Explain exactly why this happens and how you'd rewrite it.