FPGA & HDL — question 2 of 10
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You write a combinational always block for a priority encoder: `always @(*) begin if (a) out = 2'b00; else if (b) out = 2'b01; else if (c) out = 2'b10; end` -- with no final else. It simulates correctly for every case you tried where at least one of a, b, c is high. But when you load the bitstream, the board misbehaves whenever a=b=c=0, and the synthesis log has a warning you initially ignored. What is actually happening, and how would you track it down?