FPGA & HDL — question 4 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
Your RTL multiplies two 16-bit signals every clock cycle inside a small filter block. After synthesis, the resource utilization report shows 0% DSP block usage but LUT usage has jumped to nearly 40% of the device. What likely happened, and what would you check to fix it?