FPGA & HDL — question 5 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
You need a 1024-deep, 8-bit-wide lookup table in your RTL, so you declare `reg [7:0] mem [0:1023];`, write to it in one always block, and read from it combinationally elsewhere in the same module. After synthesis, the resource utilization report shows thousands of extra LUTs and flip-flops consumed, and zero block RAM used. Why did the tool build this out of fabric logic instead of using the FPGA's dedicated memory blocks, and what would you check or change?