FPGA & HDL — question 6 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
Use: required arrival time = period - setup - uncertainty; the path fails if data arrival time (Tco + logic delay) exceeds that.
A timing report shows a register-to-register path with: clock-to-out delay of the source flip-flop = 0.6 ns, combinational logic + routing delay = 3.8 ns, destination flip-flop setup time = 0.4 ns, and clock uncertainty (skew + jitter budget) = 0.3 ns. Your design's clock constraint requires a 200 MHz clock (5.0 ns period). Compute the actual maximum achievable frequency for this path and state whether the 200 MHz constraint is met.
This one resolves to a number. Give the value in the field below and your reasoning in the box — the number is checked exactly, by arithmetic.