PCB Bring-Up & Debug — question 5 of 10
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Assume you have a two-channel scope and the board's power sequencer is configurable via resistor straps or firmware.
A board has a 1.0V core rail and a 3.3V I/O rail. The datasheet requires the core rail to reach 90% of nominal before the I/O rail turns on, with the two enables no more than 5ms apart. You scope both rails on power-up, triggered on the same event, and see the I/O rail cross its threshold 2ms before the core rail even reaches 0.5V. The board intermittently fails to enumerate on USB. How do you confirm sequencing is actually the cause, and what could happen inside the chip if this violation persists?