Manufacturing, DFM & DFT interview questions

10 questions, easiest first

1. 1You've finished a board layout for a small sensor module that will be built on a multi-up panel. Your manufacturing partner asks you to add a few millimeters of blank space around every component near the board's outer edge, and to place three small copper crosses on three corners of the board. Why would they ask for this, and what happens on the line if you ignore it?intro

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   The edge clearance protects components from mechanical stress during depanelization — when a panel is broken along a v-score or mouse-bite tabs are routed out, there's flex and shock right at the board edge, and a component placed too close can crack solder joints or the part itself. The fiducials are optical alignment marks: the pick-and-place machine's camera uses them to precisely locate the panel and each board on it before placing parts, which matters a lot for fine-pitch components. If I ignore the clearance I risk cracked or tombstoned parts near the edge; if I ignore fiducials, placement accuracy suffers across the whole panel, especially for anything fine-pitch, leading to shorts or opens.

   • Explains edge clearance purpose — States that keep-out near board edges prevents components from being damaged/cracked when the panel is broken apart (v-score, routed tabs, or mouse-bites).
   • Explains fiducial purpose — States that the copper crosses are fiducials used by the pick-and-place machine's vision system to align the board/panel before placement.
   • Identifies consequence of ignoring both — Describes concrete line consequences: cracked or lifted components at depanelization, and placement shift/misalignment errors without fiducials.

   Where answers go wrong: Confusing fiducials with test points or tooling holes. · Treating edge clearance as purely cosmetic rather than a mechanical stress issue. · Failing to connect the request to what physically happens during panel separation or placement.

2. 2You've just gotten reflow-soldered prototype boards back from assembly, and you notice a handful of 0402 resistors are standing up on one end with the other pad unsoldered -- a defect called tombstoning -- instead of lying flat and soldered on both pads. Walk me through why this happens during reflow and what you'd change in the footprint or process to prevent it on the next spin.intro

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   Tombstoning happens because during reflow, solder on one pad melts and wets slightly before the other. Surface tension on the wetted side pulls the tiny part upward faster than the other pad can hold it down, so it stands on end. The usual design-side cause is a thermal mass mismatch -- one pad ties into a large ground or power plane with no thermal relief and heats up slower, while the other pad is isolated and heats faster, so they don't wet at the same time. I'd check the footprint for symmetric pad size, add thermal relief spokes on any pad connected to a plane, make sure the stencil apertures match on both sides, and if it's a real profile issue, look at extending the soak time so the whole board reaches reflow temperature more uniformly before spike.

   • Explains the physical mechanism — States that tombstoning happens because one pad's solder wets and pulls the part before the other side solidifies, creating an unbalanced surface-tension force that lifts the component.
   • Identifies a root cause tied to layout, not just process — Names at least one design-side cause such as unequal copper thermal mass (e.g., one pad tied to a ground plane without thermal relief), asymmetric pad size, or mismatched stencil apertures.
   • Proposes concrete design fixes — Suggests symmetric pad geometry, thermal relief spokes on pads connected to planes, matched stencil aperture sizing, or reviewing/adjusting the reflow soak profile.
   • Does not treat it as purely an assembly-house error — Recognizes the design itself can cause or worsen tombstoning rather than attributing it solely to operator or machine error.

   Where answers go wrong: Blaming it entirely on the assembly house or machine calibration without considering the footprint design. · Describing tombstoning as a functional or electrical defect rather than a soldering/thermal phenomenon. · Not mentioning pad symmetry or thermal relief as the actual design lever.

3. 3On the production line, an in-circuit tester (bed-of-nails) reports intermittent failures on a board that works fine when you test it by hand with a multimeter and an external power supply. The board has an edge connector but no dedicated test pads on the power rail. What's your first hypothesis, and how would you confirm it?easy

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   My first hypothesis is a test access problem, not a real electrical fault, because the board passes when I probe it by hand but fails on the fixed bed-of-nails. A hand probe can be nudged around to find a good contact point on a via or trace edge, but a pogo pin fixture is rigid and needs a dedicated, solder-mask-free, reasonably sized pad in an exact location to make repeatable contact — if that net only has a via or a thin trace instead of a proper test pad, you'll get intermittent opens under the fixture. To confirm, I'd pull the ICT failure log to see exactly which net and pin is failing, physically inspect that pad on a failing board under a scope or microscope, check the fixture's pin alignment against the pad, and try cleaning or swapping that specific pogo pin. If the same board then passes, that confirms it's a fixturing/test-access issue rather than a design defect.

   • Identifies test-point/probe-contact hypothesis — Proposes that the failure is likely due to inadequate or missing dedicated test pads causing unreliable pogo-pin contact, not a real electrical fault.
   • Distinguishes hand-probing from fixture probing — Explains why a human with a multimeter can find contact where a fixed bed-of-nails cannot (a person adjusts probe position/pressure; a fixture is fixed).
   • Gives a concrete confirmation method — Names a specific check: reviewing the ICT failure log for the exact net, inspecting/measuring the physical test pad and pin alignment, swapping or cleaning the pogo pin, or re-running with a hand probe on the same fixture pad.

   Where answers go wrong: Jumping straight to 'bad component' or 'solder defect' without considering the test access itself. · Ignoring the fact that the hand-tested board passed, which strongly points away from a component-level fault. · Not proposing any concrete way to confirm the hypothesis.

4. 4You're selecting a resistor for a current-sense circuit that will see up to 500mA continuously in an enclosure that can reach 70C ambient. The datasheet lists a 1/10W (0.1W) power rating at 25C with a derating curve that linearly drops to 0W at 125C ambient. If the resistor dissipates 60mW at your worst-case current, would you approve this part for the design as-is? Walk through your reasoning.easy

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   No, I wouldn't approve it as-is. The 0.1W rating is only valid at 25C ambient; the datasheet's derating curve says it linearly drops to zero at 125C, so at 70C ambient the usable power is roughly (125-70)/(125-25) times 0.1W, about 55mW. My actual dissipation is 60mW, which already exceeds that derated capability before I even add margin for tolerance, aging, or localized hot spots inside the enclosure. Comparing against the headline 100mW number would be the wrong move — that's a classic derating mistake. I'd fix it by picking a higher power-rated package, lowering the sense resistance to cut dissipation, or improving the thermal path with more copper pour, and I'd want the design to run at maybe 50-70% of the derated rating for margin, not right at the edge.

   • Computes derated power capability at 70C — Correctly interpolates the linear derating curve from 0.1W at 25C to 0W at 125C to find the usable power rating at 70C (roughly 0.055W).
   • Compares dissipation to derated capability with margin, not headline spec — Recognizes that 60mW exceeds or barely meets the ~55mW derated capability at 70C, so the part should not be approved as-is even though 60mW is well under the 100mW headline rating.
   • Proposes a concrete fix — Suggests a specific mitigation such as a higher power-rated part, a lower resistance value, splitting current across parallel sense resistors, or improving thermal path/copper area.

   Where answers go wrong: Comparing 60mW only against the 25C headline rating of 100mW and approving the part without derating. · Doing the derating math but not applying any additional safety margin. · Not proposing a concrete corrective action after identifying the problem.

5. 5A board uses boundary-scan (JTAG) testing to verify the solder connections on a BGA processor, and boundary scan reports the chip is fully connected with no opens or shorts. During functional test afterward, the board still fails. Why would boundary scan pass while functional test fails, and what does that tell you about what boundary scan actually verifies versus what it can't?easy

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   Boundary scan only verifies that the pins of the BGA are electrically connected the way the netlist says they should be -- it toggles boundary cells and checks for opens, shorts, and stuck-at faults on the scan-enabled nets. It doesn't exercise the chip's internal logic, analog circuitry, power rails, or timing margins, and it can't see nets that aren't part of the scan chain at all, like analog test points or power/ground. So a board can have perfect interconnect and still fail functional test because of a firmware bug, a marginal clock, bad power sequencing, or an analog fault. This tells me structural tests like boundary scan and functional tests are complementary, not overlapping -- I'd want both in a test plan, and if functional test fails with clean boundary scan, I'd look next at power integrity, clock signals, and firmware/boot behavior.

   • States boundary scan's actual scope — Correctly explains boundary scan checks digital pin-level connectivity (shorts/opens/stuck-at) on scan-enabled nets, not the chip's internal function.
   • Explains why it can pass while function fails — Gives a specific reason such as an analog/power net not covered by scan, a timing margin issue, a firmware/logic bug, or a fault outside the scan chain's boundary.
   • Distinguishes structural test from functional test — Articulates the general principle that structural/connectivity tests and functional tests catch different fault classes and neither alone gives full coverage.
   • Suggests what to check next — Names a next diagnostic step, e.g. checking power rail integrity, clock signal quality, or firmware/boot sequence.

   Where answers go wrong: Treating boundary scan and functional test as redundant rather than complementary. · Assuming boundary scan checks the chip's internal logic function. · Not recognizing that analog nets and power rails typically aren't part of the scan chain.

6. 6A new board design starts production and the first-pass functional test yield is 82% across 500 units, with failures spread across five different failure modes, none dominant. A month later, after two firmware and one BOM revision, yield is still 82% but now 90% of failures are a single mode: a specific connector intermittently failing continuity test. Is this a design problem or a process problem, and what's your next investigative step?medium

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   The fact that overall yield held at 82% while the failure modes collapsed from five scattered ones down to one dominant connector issue tells me the firmware and BOM changes successfully fixed the other root causes, and now this connector is the one thing standing between us and a much higher yield. A single, specific connector intermittently failing continuity across many units, especially since it didn't move with firmware or BOM revisions, points me toward a process or incoming-part issue rather than a schematic defect — things like inconsistent seating force in the pick-and-place or press step, solder paste volume on that footprint, or a connector lot with tighter-than-normal tolerances. It's not impossible that the footprint itself has marginal land pattern tolerances, so I wouldn't rule out design entirely. My next step would be to pull placement/SPC data for that specific connector, X-ray or cross-section a handful of failing units to see if it's a solder joint issue or a mechanical seating issue, and check whether failures cluster by date code, connector lot, or specific machine/operator to separate a process drift from a design margin problem.

   • Reads the trend correctly — Recognizes that overall yield staying flat while failure modes consolidate to one dominant mode means the other root causes were successfully fixed by prior revisions, isolating the connector as the remaining issue.
   • Reasons toward process rather than pure design defect — Argues that a single connector failing intermittently on continuity, especially after unrelated fixes, suggests a process/assembly variation (placement, solder, seating, incoming part lot) rather than a schematic error, while acknowledging it could still be a marginal footprint/tolerance design issue.
   • Names a concrete next investigative step — Proposes a specific action: pull SPC/placement data for that connector, cross-section or X-ray failing units, check if failures cluster by date code/lot/machine/operator, or compare against the connector's mechanical datasheet tolerances.

   Where answers go wrong: Declaring it purely a design problem or purely a process problem without evidence. · Ignoring that the failure mode consolidation itself is diagnostic information. · Not proposing any way to actually gather more data before concluding.

7. 7You're choosing a microcontroller for a new design. Option A is a well-documented, single-source part from a manufacturer with a history of long lead times and occasional allocation shortages, but it has more memory and a lower unit cost. Option B is a slightly more expensive, slightly less capable part but is available from two independent manufacturers with pin-compatible drop-in variants. The product is expected to ship for 5+ years. Which do you pick, and what would change your answer?medium

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   For a product shipping 5+ years, I'd lean toward Option B, the second-sourced part, even at a slightly higher unit cost and slightly lower capability, because supply continuity matters more than a small BOM cost delta over that kind of lifetime. A single-sourced part going on allocation or being discontinued can halt production entirely and force a redesign and requalification, which costs far more in engineering time and lost sales than the unit price savings ever would. That said, this isn't absolute — if we're building at very high volume with thin margins where the unit cost difference adds up to real money, or if Option A's extra memory is something the product genuinely can't do without and there's no equivalent elsewhere, I'd reconsider and might mitigate the single-source risk with a larger buffer stock or a qualified backup design instead. I'd also want to verify that Option B's two sources are truly pin- and function-compatible, not just marketed that way, before trusting it as real second-sourcing.

   • Weighs supply risk against unit economics — Explicitly compares the cost/capability advantage of the single-sourced part against the business risk of a shortage or EOL event over a 5+ year production run.
   • Gives a reasoned pick with justification — States a clear choice (typically Option B for a long-lived product) and justifies it in terms of supply continuity rather than just repeating both options.
   • Identifies conditions that would flip the decision — Names at least one concrete factor that would change the answer, such as very high volume with tight margins where unit cost dominates, a short product life, or if Option A's extra memory is functionally required and unavailable elsewhere.

   Where answers go wrong: Picking purely on unit cost or purely on capability without addressing supply risk. · Treating the decision as absolute rather than dependent on volume, margin, and product lifetime. · Not mentioning that a shortage can cost far more than the unit price difference in redesign/requalification effort.

8. 8A product line has been running steadily at 95% first-pass yield for the past three months. Over the last two weeks, yield has slid down to about 70%, and nearly every failing board fails the same in-circuit test step on one particular component footprint. Walk me through how you'd figure out whether this is a design flaw that's been latent all along, or a process change that just started, and what data you'd pull first.medium

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   A sudden drop after three months of stability is a strong signal this is a process or supply change, not a latent design flaw -- a design defect would usually show up from day one, maybe at a lower steady rate, not appear suddenly after months of good yield. So first I'd pull the timeline: exactly when did the drop start, and what changed around that date -- new component lot or date code on that footprint's part, a solder paste lot change, stencil wear or replacement, reflow profile edits, or even a shift/operator change. Then I'd compare failing boards against boards built in the same window that passed, and against archived boards from before the drop, to isolate what's actually different -- same design, different lot, different result would confirm a process/component issue. Only if I found the design was equally likely to fail across all time periods, just masked by margin, would I escalate it back to a design review.

   • Uses the stable-then-sudden-drop pattern as a diagnostic clue — Explicitly reasons that three months of stable yield followed by a sudden two-week drop points toward something changing in the process/supply chain rather than a static design defect.
   • Names concrete data sources to pull — Specifies checking component lot/date codes, solder paste lot changes, stencil condition, reflow profile logs, or any process/equipment changes around the failure onset date.
   • Proposes a comparison to isolate the variable — Suggests comparing failing units to passing units from the same period, or comparing recent failures to boards built before the drop, to narrow down what actually changed.
   • Distinguishes design vs process framing — Clearly separates what evidence would indicate a design issue (present since day one, would show at low but nonzero rate earlier) from process issue (correlates with a specific change event).

   Where answers go wrong: Jumping straight to 'redesign the footprint' without first checking for a process or component change. · Not asking for lot/date code or process log data, treating the fix as purely electrical. · Ignoring the significance of the sudden onset after months of stability, treating it like the earlier long-running 82% multi-mode yield case.

9. 9You're designing test access for a densely populated board with no room for a full bed-of-nails fixture on 30% of nets, including several fine-pitch BGA power and signal pins. You have a budget for at most 8 dedicated test points and one boundary-scan-capable device already on the board. Describe the test strategy you'd propose, including what you'd verify with each method and what would still go untested.hard

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   I'd use the boundary-scan device to cover as many of the inaccessible BGA digital nets as possible, since it can verify interconnect continuity and detect shorts/opens on a chain without needing physical probe access — that's exactly the gap it's built for. I'd spend the 8 dedicated test points on things boundary scan can't touch: the power rails and ground references, since a bad power net can cascade into failures everywhere and is critical to catch early, plus any critical analog or mixed-signal nets that have no other verification path. What I'd explicitly flag as untested or under-tested is analog performance and signal integrity — boundary scan only tells you the connection exists, not that a signal meets its timing or level requirements — and I'd also call out that solder joint quality on the BGA itself, especially hidden balls, isn't fully proven by boundary scan alone. To close that gap I'd push for AOI or X-ray sampling on the BGA during process qualification and rely on functional test at final test to catch anything electrical that structural test methods miss, being upfront that this combination reduces risk but doesn't guarantee zero escapes.

   • Uses boundary scan appropriately — Proposes using the existing boundary-scan-capable device to verify BGA interconnect continuity/shorts on digital nets that a physical probe can't reach, correctly identifying what boundary scan can and cannot check (e.g., no analog verification).
   • Allocates the 8 test points strategically — Prioritizes the limited physical test points for power rails, ground references, or critical nets that boundary scan can't cover, rather than spreading them arbitrarily.
   • Explicitly names untested/under-tested coverage gaps — Identifies specific classes of nets or failure modes that remain unverified by this strategy (e.g., analog performance, timing margins, mechanical solder joint quality) rather than implying full coverage.
   • Proposes a mitigation for the gap — Suggests a supplementary method for the gap such as functional/in-application test, AOI, X-ray sampling, or a follow-on burn-in/qual step.

   Where answers go wrong: Treating boundary scan as a full replacement for physical test access without noting its limits (digital-only, doesn't verify analog behavior or timing margins). · Spreading the 8 test points evenly across all inaccessible nets rather than prioritizing power and critical signals. · Claiming full test coverage without acknowledging any gap.

10. 10You're designing a calibrated temperature-measurement circuit that depends on a precision voltage reference with a tempco of 5 ppm/°C, calibrated at 25C, and used across an operating range of -20C to 70C. Your sourcing contact says the primary reference has a 26-week lead time, but there's a pin-compatible drop-in alternate with a tempco of 25 ppm/°C. Walk me through how you'd decide whether to qualify the alternate, and roughly how much extra calibration error it introduces across the operating range.hard

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    Tempco error is relative to the calibration point, so what matters isn't the full 90C span from -20 to 70, it's the largest excursion from 25C, which is 45C on the hot side and 45C on the cold side -- so 45C either way. The tempco difference between the two parts is 20 ppm/C, so the alternate adds roughly 20 times 45, about 900 ppm, or 0.09% extra error compared to the primary part across the operating range. Whether that's acceptable depends on the system's total error budget -- if the design has margin after accounting for initial accuracy, aging, and ADC error, an extra 0.09% might be fine; if the budget is tight, it could push the design out of spec. I'd pull the error budget, add this in, and if it doesn't fit, look at either firmware compensation, tightening calibration, or accepting the 26-week lead time risk on the primary part while qualifying the alternate as a backup for later.

    • Correctly identifies the relevant temperature delta — Uses the excursion from the 25C calibration point (45C on either side, since -20 to 70 spans 45C below and above 25C) rather than the full 90C span.
    • Computes the extra error correctly — Calculates additional error as the tempco difference (20 ppm/C) times 45C, arriving at roughly 900 ppm or about 0.09% extra error versus the primary part.
    • Frames the decision as an error-budget question — States that qualifying the alternate depends on whether the total error budget (tempco plus other sources like initial tolerance, aging, ADC) still meets spec, not just on the tempco number alone.
    • Weighs the lead-time/single-source risk explicitly — Acknowledges the tradeoff between accepting the accuracy hit now versus risking a 26-week supply gap, and considers options like qualifying both parts or adding compensation.

    Where answers go wrong: Using the full 90C span instead of the 45C excursion from the calibration point. · Treating the tempco spec as the total error budget rather than one component of it. · Deciding purely on lead time or purely on accuracy without considering the system error budget as the actual pass/fail criterion. · Forgetting that calibration at 25C changes what 'temperature range' means for tempco error.