PCB Design — question 10 of 10
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Board is otherwise routed and ready for review; adding layers is off the table due to cost and schedule.
You're doing a design review on a 4-layer board: layer 1 signal, layer 2 solid ground, layer 3 power (split between a 5V rail and a 3.3V rail), layer 4 signal. A high-speed differential pair runs on layer 1 with its return path on the solid layer 2 ground -- that part is fine. But a separate single-ended 100MHz clock trace on layer 4 references layer 3 as its return plane, and it crosses directly over the split between the 5V and 3.3V regions on layer 3. What problems would you expect from this, and how would you fix it without adding layers?