PCB Design interview questions

10 questions, easiest first

1. 1A trace on an outer copper layer is 20 mils wide, 1oz copper, and you're allowed a 20°C temperature rise above ambient. Using the IPC-2221 style external-layer current-capacity relationship, estimate roughly how much continuous current that trace can carry. Walk me through your reasoning, not just a number pulled from a chart.intro

   IPC-2221 gives an empirical relation for external layers: I = k * (ΔT)^0.44 * A^0.725, where k≈0.048, ΔT is temperature rise in °C, and A is cross-sectional area in mil².

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   First I convert width to area: 20 mils wide times 1oz copper thickness (~1.4 mils) gives roughly 28 mil² of cross-section. Plugging into I = 0.048 * (20)^0.44 * (28)^0.725: 20^0.44 is about 3.7, so k*ΔT^0.44 ≈ 0.18. Then 28^0.725 is roughly 11-12, so I comes out around 2A. I'd treat that as a rough starting point -- for a real board I'd add margin for the fact that internal layers dissipate heat worse, other traces nearby add heat, and I'd want some safety factor rather than running right at the calculated limit.

   • Computes cross-sectional area — Converts width x copper thickness (~1.4 mil for 1oz) into an area in mil^2 rather than using width alone
   • Applies the power-law formula — Correctly uses I = k*ΔT^0.44*A^0.725 to land on an estimate in the right ballpark (roughly 1.5-2.5A)
   • Flags this as an estimate needing margin — States that this is an empirical starting point and a real design should derate for internal layers, altitude, or nearby traces
   • Understands rise vs absolute temperature — Correctly treats ΔT as a rise above ambient, not an absolute temperature limit

   Where answers go wrong: Treats trace width alone as the cross-sectional area without accounting for copper thickness · Uses the internal-layer k constant for what is explicitly an external trace · Reports a single 'chart value' without showing the reasoning that produced it

2. 2You're laying out a board with an MCU that needs an external 16MHz crystal for its clock. Board space near the MCU is tight, so you're considering placing the crystal about 3 inches away, running traces to it, and using a couple of vias to route under other components. Would you do this? Walk me through your reasoning.intro

   Assume standard 2-layer hobbyist-style board, no ground plane between crystal and MCU other than what you design in.

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   No, I wouldn't do that. Crystal traces aren't just wires -- they're part of a resonant circuit with the crystal's load capacitors, so extra trace length adds parasitic capacitance and inductance that can shift the oscillation frequency, reduce margin, or in bad cases prevent startup entirely. They're also unshielded, high-impedance nets, so a longer run with vias increases the chance of picking up noise from nearby digital signals or radiating noise itself, which is worse with vias adding inductive stubs. My approach would be to place the crystal and its load caps as one of the very first things in placement, right next to the MCU's oscillator pins, keep the traces short and symmetric, avoid vias on that net entirely if possible, and surround it with ground copper. If space is genuinely impossible, I'd reconsider the MCU orientation or connector placement before compromising the clock circuit.

   • identifies-parasitic-risk — States that longer/via'd crystal traces add parasitic capacitance/inductance that can shift oscillation frequency or prevent reliable startup.
   • identifies-noise-susceptibility — Notes the crystal traces are high-impedance and unshielded, so extra length and vias increase susceptibility to EMI/crosstalk from nearby traces.
   • gives-concrete-recommendation — Recommends placing the crystal immediately adjacent to the MCU pins and reserving that placement early, rather than routing to it later.
   • mentions-guard-or-ground — Mentions surrounding the crystal traces with ground pour/stitching or keeping other signals away as a mitigation if some distance is unavoidable.

   Where answers go wrong: Treating the crystal net like any other digital signal that can be routed anywhere with enough copper. · Not mentioning that vias add inductance and stubs that matter more at MHz-range oscillator frequencies than DC nets. · Suggesting a fix (like a buffer or clock IC) that's overkill for the situation instead of the simple placement fix.

3. 3You've built a board with a microcontroller and a 12-bit ADC reading a sensor. The digital side works fine, but the ADC readings show several LSBs of noise that seem to track with when the MCU toggles a nearby GPIO or drives an SPI bus. Walk me through how you'd confirm this is a grounding/return-current issue and what you'd change on the next board.easy

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   I'd first confirm correlation before changing anything: scope the ADC's ground reference, or read a spare ADC channel tied to a known DC voltage, while deliberately toggling the GPIO or running SPI traffic, and see if the noise lines up with switching edges. If it does, the likely cause is a shared return-current path -- digital switching current flowing through the same plane region the analog signal references, causing local voltage drops that show up as ADC noise. On the next revision I'd keep the ground plane solid but be deliberate about placement: group analog components together, route digital switching traces and vias away from that region, and connect the two areas at a single point near the ADC's reference. I'd also reconsider whether SPI/GPIO current loops are routed near or under the analog section, and add a ferrite or RC filter on the ADC's supply if the correlation persists.

   • Proposes a measurement to confirm correlation — Suggests scoping the ADC's ground reference or a spare channel while deliberately toggling the GPIO/SPI to see if noise timing correlates with switching edges
   • Identifies shared ground impedance as the likely cause — Names shared return-current path / ground bounce specifically, rather than just saying 'noise' or 'interference'
   • Proposes a concrete layout fix — Suggests partitioning analog/digital placement, keeping switching traces away from the analog region, and/or a single-point ground connection near the ADC
   • Avoids blindly cutting the plane — Recognizes that splitting the ground plane without a deliberate single connection point can make return-path issues worse, not better

   Where answers go wrong: Immediately cutting the ground plane to 'separate' analog and digital without a single connection point · Assuming it's power supply noise without first checking correlation to digital switching activity · Adding a capacitor somewhere without first diagnosing the actual coupling path

4. 4A regulator on your board has its output decoupling capacitor on the schematic, and it's populated on the board, but you're seeing voltage droop and brief resets on a downstream digital load during current transients. The cap value and ESR look fine on paper. What would you check about the physical placement, and why might placement alone cause this?easy

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   The cap's value and ESR only describe part of the picture -- what matters during a fast transient is the total loop inductance between the cap and the load's actual power/ground pins, which comes from trace length, via count, and how directly it connects to plane. If the regulator's output cap sits near the regulator but far from the digital load, current has to travel through extra inductance to reach the load during a fast step, causing a dip the cap's spec sheet doesn't predict. I'd add a separate local bypass cap directly at the load's power pins with minimal vias and a short connection to plane, and treat the regulator's output cap as bulk/stability capacitance rather than the fast-transient supply. To confirm, I'd scope directly at the load's supply pin during a load step and see whether the dip magnitude tracks with routing distance from the existing cap.

   • Identifies loop inductance from placement — Names the physical distance/via count between the cap and the load's power-ground pins as introducing series inductance not reflected in the cap's spec
   • Proposes a concrete placement fix — Suggests moving a cap closer to the load, minimizing vias/trace length in the path, or connecting directly to plane
   • Distinguishes bulk vs local decoupling — Recognizes the regulator output cap and a load-local cap serve different roles and one placement can't cover both
   • Proposes a measurement to verify — Suggests scoping directly at the load's power pin during a load transient to confirm the dip location

   Where answers go wrong: Assumes the cap's rated value/ESR alone determines transient response regardless of where it sits · Confuses the regulator's stability capacitor with the load's local decoupling capacitor · Ignores via inductance in the power delivery path

5. 5A buck regulator on your board needs to deliver 3A from its output pad down through vias to a power plane on an inner layer. Using a common rule of thumb that a standard 0.3mm (12 mil) finished-hole via can safely carry roughly 1A with an acceptable temperature rise on a typical 2oz board, how many vias would you place in parallel, and why would you not just use the bare minimum number?easy

   Assume the via and pad geometry is otherwise standard, and you're deciding a layout detail before routing the power stage.

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   At 1A per via, 3A needs at least 3 vias as a bare minimum, but I wouldn't stop there -- I'd use 4 to 6 in parallel. The rule of thumb already assumes ideal plating and moderate ambient conditions, and a regulator's output node is right next to a heat-generating part, so the real temperature rise per via will likely be higher than the rule of thumb assumes. More vias also protect against one via having a plating defect or crack from thermal cycling, which would silently push more current through the remaining vias and could cascade into failure. It's a cheap insurance policy -- vias cost almost nothing in board area or fab cost compared to the risk of an undersized power path.

   • correct-via-count-reasoning — Computes roughly 3 vias as the bare minimum for 3A at ~1A/via, showing the division reasoning explicitly.
   • adds-margin — Explicitly recommends more than the bare minimum (e.g., 4-6 vias) rather than stopping at exactly 3.
   • justifies-margin — Gives a real reason for margin: redundancy if one via is defective, reduced temperature rise per via, or accounting for the regulator's own heat adding to the rise.

   Where answers go wrong: Answering with exactly 3 vias and treating that as final without discussing margin. · Not connecting via current capacity to temperature rise, treating it as a fixed spec with no derating context. · Ignoring that the regulator itself is a heat source that reduces the safe margin for the vias near it.

6. 6You're doing a schematic review before a board goes to layout. It's an I2C bus with two sensors and the MCU, all at 3.3V. The schematic shows SDA/SCL routed correctly to each device, appropriate decoupling, and correct part numbers. What's the one thing you'd specifically hunt for on an I2C schematic that's easy to miss and would make the bus fail silently until you scope it, and how would you catch it before fabrication?medium

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   I'd specifically check for pull-up resistors on SDA and SCL, since I2C devices are open-drain and the bus won't function at all without them -- yet a schematic can look complete with correct nets and part numbers while omitting pull-ups entirely, especially if someone assumes the MCU provides internal ones by default. I'd also check whether more than one device's schematic block includes its own pull-up recommendation from its datasheet; if two sensors and the MCU each add a 4.7k pull-up, the effective parallel resistance drops well below what was intended, which can blow past drive current limits or hurt rise-time margin even though the bus 'technically' pulls high. To catch it before fab, I'd trace SDA/SCL specifically looking for exactly one set of pull-ups sized for the total bus capacitance and target speed, and do a quick R*C rise-time estimate against the I2C spec for the clock rate we're using.

   • Identifies missing or duplicated pull-ups — States that I2C is open-drain and needs external pull-ups on SDA/SCL, and notes this is commonly missed or accidentally duplicated when multiple devices are added
   • Checks value against bus loading/speed — Mentions verifying the pull-up value against total bus capacitance and target clock speed for adequate rise time
   • Notes stacking from multiple devices — Recognizes that if each device's datasheet-recommended pull-up is independently populated, the effective parallel resistance can end up too low
   • Proposes a concrete verification method — Describes tracing SDA/SCL nets specifically for pull-ups before fab, or estimating rise time (R*C) against the I2C spec for the target speed

   Where answers go wrong: Assumes correct part numbers and net connections mean the bus will work · Doesn't consider that multiple devices might each add their own pull-up, stacking to too low an effective resistance · Copies a pull-up value from a reference design without checking it against actual bus capacitance/speed

7. 7You're planning the stackup for a board with an MCU, a few high-speed digital signals (a ~50MHz clock and a fast serial bus), and a sensitive analog front end. You're choosing between a 4-layer stackup (signal/ground/power/signal) and a 6-layer stackup with dedicated ground and power planes plus more routing layers. Walk me through the tradeoffs and what would push you toward one or the other on a board like this.medium

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   At 4 layers (signal-ground-power-signal), I get one solid reference plane pair adjacent to each signal layer, which is workable if I'm careful -- keeping the analog section physically separate, routing the fast serial bus and clock over the ground layer with minimal layer changes, and not overloading routing density to the point I'm tempted to split the ground plane to route power. The risk is that a tight board fills the signal layers with digital routing that ends up near the analog front end, or a plane split hurts return current continuity right under the fast signals. A 6-layer stackup gives a dedicated, uninterrupted ground plane, separate power planes, and more routing layers so digital and analog routing don't have to share a layer, plus better impedance control for the fast serial bus since it can have its own consistent reference. I'd push for 6 layers if routing density is high or the analog front end is sensitive enough that I don't trust keeping it clean at 4; I'd stay at 4 if I can route without compromising the ground plane and cost/lead time matters more, since more layers directly adds cost and fab time.

   • Explains what 4-layer gives you — Notes 4-layer gives one ground/power reference pair adjacent to signal layers, workable for moderate speed/analog if carefully planned
   • Explains what 6-layer buys you — Notes extra layers allow a dedicated uninterrupted ground plane, more routing freedom to separate analog/digital, and better impedance control for the fast serial bus
   • Ties the decision to this board's specific constraints — Connects the choice to actual factors like routing density/escape feasibility at 4 layers, whether adequate analog isolation is achievable, and cost sensitivity
   • Treats it as a genuine tradeoff — Discusses cost, lead time, and complexity as real downsides rather than defaulting to 'more layers is always better'

   Where answers go wrong: States that 6-layer is simply 'better' without weighing cost or lead time · Assumes more layers automatically fixes noise coupling without still needing good placement discipline · Ignores routing density as a real driver of the decision

8. 8You're reviewing a schematic before it goes to layout. The MCU's RESET pin connects to a push-button to ground and a 0.1uF capacitor to ground for debounce, but there's no external pull-up resistor to VCC anywhere on that net. The MCU's datasheet says RESET has an internal weak pull-up that is 'typically enabled' but gives no guaranteed minimum pull-up current or resistance in the electrical characteristics table. Would you sign off on this schematic as-is? What's your reasoning?medium

   This is a pre-fab schematic review; the board is otherwise fully designed and ready to send to layout.

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   I would not sign off on it as-is. The datasheet only says the internal pull-up is 'typically enabled' with no guaranteed minimum current or resistance in the electrical table, which means I can't rely on it across process variation, temperature, or even different die revisions of the same part. If that pull-up turns out weaker than expected, or is configurable and gets disabled by a fuse or firmware setting, the RESET line would be left floating with only a debounce cap holding a rough level -- that's a recipe for spurious resets from noise coupling onto that trace, or worse, the MCU not reliably coming out of reset. The fix is trivial: add an external pull-up resistor, something like 4.7k to 10k to VCC, in parallel with the switch and cap. It costs one resistor and removes any dependency on an unguaranteed internal feature. I'd flag this in the review and hold the schematic until it's added.

   • flags-the-missing-pullup — Identifies that the missing external pull-up is the specific issue, not a vague 'looks okay' or unrelated concern.
   • questions-datasheet-guarantee — Explicitly reasons that a 'typical' spec without min/max guarantee is not something to design around.
   • describes-failure-mode — Describes a plausible resulting failure: floating reset line, spurious resets from noise, or failure to release reset reliably.
   • proposes-concrete-fix — Recommends adding an external pull-up resistor (with a reasonable value like 4.7k-10k) rather than a vague 'add more testing' answer.

   Where answers go wrong: Assuming the internal pull-up is sufficient because the datasheet mentions it exists, without checking for a guaranteed spec. · Focusing only on debounce capacitor value and missing the actual pull-up gap entirely. · Suggesting a redesign of the whole reset circuit instead of the simple, targeted fix.

9. 9Your board has a solid ground plane on layer 2, but a connector and some through-hole mounting hardware force a keepout that splits the ground plane into two regions for about an inch, right under a differential signal pair that has to cross that gap. What actually happens electrically when the signal's return current hits that gap, and what would you do about it given you can't move the connector?hard

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   When the reference plane has a gap under a trace, the return current can't continue on its direct path directly beneath the trace -- it has to detour around the split, which increases the effective loop area for that signal, creates an impedance discontinuity right at the gap, and raises radiated emissions and crosstalk risk there. For a differential pair specifically, the fields are mostly concentrated between the two traces, so the effect is somewhat mitigated compared to single-ended, but any common-mode component or asymmetry in propagation still needs a return path, so I wouldn't rely on differential routing alone to make the gap a non-issue. Since I can't move the connector, I'd place a stitching capacitor -- something in the 0.01 to 0.1uF range, sized to look like a low impedance at the frequencies of concern -- bridging the two ground regions as close as possible to where the pair actually crosses the gap, giving high-frequency return current a local, low-inductance path without creating a DC ground loop. If the frequencies are too high for a cap to act as a good short, I'd look at rerouting the pair to cross at the gap's narrowest point, or moving it to a different layer where the reference plane underneath isn't split at all.

   • Explains the electrical consequence of the gap — States that return current can't take the direct path under the trace and must detour, increasing loop area, creating an impedance discontinuity, and raising EMI/crosstalk risk
   • Addresses the differential-pair specifics — Notes that for a true differential pair the fields are concentrated between the traces, mitigating but not eliminating the issue, since common-mode/asymmetry still needs a return path
   • Proposes a stitching capacitor or via bridge — Proposes placing a stitching capacitor (or via to another return plane) across the gap right at the crossing point to give high-frequency return current a local path
   • Recognizes routing alternatives — Mentions rerouting the pair to cross at the narrowest point, or moving it to a layer with an unsplit reference plane, if stitching alone isn't sufficient

   Where answers go wrong: Assumes the plane gap doesn't matter because 'it's just ground' · Proposes moving the connector or trace without acknowledging the stated hardware constraint · Suggests a stitching cap 'somewhere on the board' without placing it at the actual crossing point

10. 10You're doing a design review on a 4-layer board: layer 1 signal, layer 2 solid ground, layer 3 power (split between a 5V rail and a 3.3V rail), layer 4 signal. A high-speed differential pair runs on layer 1 with its return path on the solid layer 2 ground -- that part is fine. But a separate single-ended 100MHz clock trace on layer 4 references layer 3 as its return plane, and it crosses directly over the split between the 5V and 3.3V regions on layer 3. What problems would you expect from this, and how would you fix it without adding layers?hard

    Board is otherwise routed and ready for review; adding layers is off the table due to cost and schedule.

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    The clock trace's return current wants to flow directly beneath it on layer 3, but the plane split blocks that path, so the current has to detour around the split -- effectively increasing the loop area of that signal right at the crossing. That shows up as increased radiated emissions at 100MHz and its harmonics, added series inductance that can round off edges or add ringing, and a higher chance of crosstalk into nearby traces near that detour. Since I can't add layers, my first choice is to reroute that specific clock trace so it doesn't cross the split at all, or move it to reference the solid layer 2 ground plane instead if there's room. If rerouting isn't practical, I'd add a stitching capacitor -- something like 0.01uF to 0.1uF -- placed right at the crossing point, bridging the 5V and 3.3V plane regions, so high-frequency return current has a local low-impedance path without actually connecting the two DC rails together. I'd want to check the crossing location precisely so the cap is placed directly under or very near the trace's crossing, not just somewhere nearby on the split.

    • identifies-return-path-issue — Correctly explains that the clock trace's return current is forced to detour around the plane split, not just states 'it's bad' without the mechanism.
    • names-consequences — Names concrete consequences: increased EMI/radiated emissions, added loop inductance, possible signal integrity or timing issues, or crosstalk into nearby nets.
    • proposes-stitching-cap-fix — Proposes a stitching capacitor across the split at the crossing point as a fix that doesn't require rerouting or adding layers.
    • proposes-reroute-alternative — Also considers rerouting the trace to avoid the split or moving it to reference the solid ground layer as a preferred or alternative fix.

    Where answers go wrong: Saying only 'it will cause noise' without explaining the return-current-detour mechanism. · Suggesting to just remove the plane split entirely without acknowledging that the split exists for a reason (separating two rails). · Proposing to add a layer, ignoring the stated constraint that layers can't be added.