Power Electronics — question 4 of 10
Write a real answer. It is graded against the question's rubric, and the mastery movement is computed by the same engine the product uses. Scoring here is deterministic rather than model-written, so this page costs nothing to run and nothing is saved. In a track built from your own posting, the same rubric is graded by the model, which is what produces feedback about your reasoning rather than about coverage.
The bulk cap is present and correctly sized for the average current; the droop only appears on fast edges.
You probe VCC right at a chip's supply pin during a fast digital load transient and see a several-millivolt droop that recovers within a few microseconds, even though there's a 100uF bulk capacitor a few centimeters away. What's most likely missing from the decoupling scheme, and how would you confirm it?