Power Electronics interview questions

10 questions, easiest first

1. 1You need to power a low-noise analog sensor front-end that draws about 50 mA, stepping a quiet 5V rail down to 3.3V. Would you reach for an LDO or a synchronous buck converter here, and why does that choice matter for this specific load?intro

   The input rail already has low ripple; the concern is the sensor's sensitivity to noise on its supply.

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   Or just show what a strong answer covers

   I'd use an LDO. The load is only 50mA and the drop is 1.7V, so the LDO dissipates about 85mW — trivial, no thermal concern. In exchange I get a clean, ripple-free output with no switching harmonics, which matters a lot for a sensitive analog front-end. A buck converter would be more efficient, but it switches at hundreds of kHz to MHz and that ripple, plus any EMI, would couple onto the sensor's supply and likely show up as noise on the measurement unless I added significant extra filtering. Since the power loss here is negligible, there's no efficiency argument compelling enough to justify that added complexity and risk.

   • Chooses LDO with justification — States LDO is preferable and ties the choice explicitly to the sensor's noise sensitivity, not just 'LDOs are simpler'.
   • Computes or estimates dissipation — Calculates or approximates power dissipated in the LDO (~1.7V x 0.05A ≈ 85mW) and states it's manageable without a heatsink.
   • Explains why a buck would be worse here — Mentions switching ripple/EMI from a buck could couple onto the sensor's supply and would need extra filtering to match LDO noise performance.
   • Acknowledges the tradeoff isn't universal — Notes that if the current or voltage drop were much larger, efficiency losses would force reconsidering a switcher.

   Where answers go wrong: Picking the switcher by default because 'it's more efficient' without weighing the noise-sensitive load. · Not calculating dissipation and instead just asserting the LDO 'gets too hot'. · Forgetting that a buck's noise can be mitigated with filtering, making it not an absolute rule.

2. 2A board has a fast digital IC that needs both a 10uF bulk capacitor and a 0.1uF ceramic capacitor near its supply pin, rather than just one big capacitor of some value. Explain why you'd use two different capacitor values in parallel instead of a single larger one, and how that decision affects where each part goes on the layout.intro

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   Or just show what a strong answer covers

   Each capacitor is only a low-impedance path over a limited frequency range because of its own parasitic inductance (ESL) and its physical distance from the load. The 10uF bulk cap has more capacitance so it holds impedance low at lower frequencies and supplies charge over longer transients, but its larger package and any trace length give it enough ESL that its impedance starts rising again well before you get to fast digital switching edges. The 0.1uF ceramic is physically small, has very low ESL, and its self-resonant frequency is much higher, so it's the one that can still source current on nanosecond timescales — but it doesn't have much total charge stored. Putting them in parallel gives a broadband low-impedance PDN. On layout, the 0.1uF needs to be right at the pin with the shortest possible loop to ground, because any added loop inductance there kills its high-frequency benefit; the 10uF can sit a bit further back since it's covering the slower part of the spectrum.

   • Different frequency coverage — States that the bulk cap supplies charge for slower/larger transients and the small ceramic handles fast, high-frequency transients.
   • ESL / self-resonance reasoning — Explains that a single large capacitor has more parasitic inductance and its impedance rises again above some frequency, making it ineffective at high frequency.
   • Placement rule — States the smallest/fastest capacitor should sit closest to the IC's supply pin to minimize loop inductance.
   • Rejects the single-big-cap idea explicitly — Explicitly says why one large cap alone would fail to meet high-frequency demand even if its capacitance is large.

   Where answers go wrong: Assumes a single larger capacitance value would always work just as well or better. · Never mentions parasitic inductance (ESL) or self-resonant frequency. · Forgets to connect the reasoning to physical placement on the board.

3. 3A synchronous buck converts 12V to 5V, switching at 500kHz with a 10uH inductor. Ignoring losses, what is the peak-to-peak inductor ripple current? Then tell me: if the load drops to 50mA, does the converter stay in continuous conduction mode (CCM), and what changes if it doesn't?easy

   Assume ideal duty cycle D = Vout/Vin for this estimate.

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   Duty cycle is Vout/Vin = 5/12 ≈ 0.417. Ripple current is (Vin-Vout)*D/(L*f) = 7*0.417/(10e-6*500e3) ≈ 0.583A peak-to-peak. Half of that is about 0.29A. At 50mA load, the average current is way below that 0.29A threshold, so the inductor current would try to go negative and the converter drops into discontinuous conduction mode instead. In DCM, the inductor current hits zero each switching cycle, the output ripple waveform shape changes, and the small-signal response of the loop is different, which can mean more overshoot or different compensation needs at light load compared to full load CCM operation.

   • Correct duty cycle — Computes D ≈ 5/12 ≈ 0.417.
   • Correct ripple current magnitude — Computes ΔI ≈ (12-5)*0.417/(10e-6*500e3) ≈ 0.58A within reasonable rounding.
   • Correctly identifies DCM at light load — States that since ripple/2 (~0.29A) exceeds the 50mA average load, the converter drops into DCM.
   • Explains consequence of DCM — Notes DCM causes the inductor current to hit zero each cycle, changing output ripple shape and loop response, sometimes causing extra output voltage rise or requiring different compensation.

   Where answers go wrong: Using Vin*D/(L*f) without subtracting Vout, giving a ripple current that's too large. · Confusing peak current with peak-to-peak ripple current. · Assuming light load always stays in CCM because 'that's the normal mode'.

4. 4You probe VCC right at a chip's supply pin during a fast digital load transient and see a several-millivolt droop that recovers within a few microseconds, even though there's a 100uF bulk capacitor a few centimeters away. What's most likely missing from the decoupling scheme, and how would you confirm it?easy

   The bulk cap is present and correctly sized for the average current; the droop only appears on fast edges.

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   A 100uF cap a few centimeters away is fine for slower current demand, but the trace and via inductance between it and the pin means it simply can't deliver current fast enough for a nanosecond-scale edge — its effective impedance at that frequency is too high. What's likely missing is a small ceramic capacitor, like 0.1uF or 1uF, placed as close as physically possible to the pin with a short low-inductance via to ground. I'd confirm by adding one right at the pin and re-checking the droop, or more rigorously by measuring the PDN impedance versus frequency and looking for a gap between where the bulk cap's impedance rises and where the local cap's impedance takes over.

   • Identifies missing local decoupling — States that small, close-placed ceramic capacitors are likely missing or too far from the pin.
   • Explains why distance/inductance matters — Explains that trace/via inductance between the bulk cap and the pin makes the bulk cap too slow to respond to a fast edge, regardless of its capacitance value.
   • Proposes a way to confirm — Suggests adding/moving a ceramic cap closer and re-measuring, or measuring PDN impedance vs frequency, or looking at the transient with a faster probe/higher bandwidth.
   • Distinguishes bulk vs local cap roles — Notes bulk caps address lower-frequency/larger charge reservoirs while local caps address high di/dt edges.

   Where answers go wrong: Concluding the bulk cap value is simply too small without considering placement/inductance. · Suggesting to just add more bulk capacitance rather than addressing high-frequency impedance. · Not mentioning measurement/verification, just naming a fix without a way to confirm it worked.

5. 5A synchronous buck converts 12V to 5V, switching at 300kHz with a 15uH inductor. The converter transitions from continuous to discontinuous conduction mode (CCM to DCM) when the average load current drops below half the peak-to-peak inductor ripple current. Calculate that boundary current, then explain what happens to the inductor current waveform and output behavior once you cross into DCM.easy

   Assume an ideal (lossless) converter for the duty cycle calculation.

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   Or just show what a strong answer covers

   Duty cycle D = Vout/Vin = 5/12 ≈ 0.417. Ripple ΔI = (12-5)*0.417/(15e-6*300e3) ≈ 7*0.417/4.5 ≈ 0.65A. The CCM/DCM boundary is half that, about 0.32A of average load current. Above that, inductor current is a triangle wave that never reaches zero. Below it, the inductor current would want to go negative in an ideal synchronous buck, but in practice control schemes either allow the low-side switch to turn off early or the diode/body-diode blocks reverse current, so the current sits at zero for part of the cycle — the waveform becomes a series of triangular pulses separated by dead time. Output ripple can actually increase in DCM, the small-signal transfer function changes, and many converters switch to pulse-skipping or PFM mode at light load to keep efficiency reasonable instead of running in true DCM continuously.

   • Correct ripple current calculation — Uses ΔI = (Vin-Vout)*D/(L*f) with D=Vout/Vin=5/12 to get roughly 0.65A ripple.
   • Correct boundary current — Divides the ripple by two to get a boundary average load current around 0.32A (320-330mA).
   • Describes DCM waveform shape — Explains that below the boundary, inductor current reaches zero and dwells there for part of the cycle rather than reversing, changing the waveform from triangular-continuous to a discontinuous pulse.
   • Practical consequence — Notes real-world effects like increased ripple voltage, altered small-signal behavior, or that many converters switch to pulse-skipping/PFM at light load to maintain efficiency.

   Where answers go wrong: Forgetting to compute duty cycle from Vout/Vin before plugging into the ripple formula. · Reporting the peak ripple current instead of dividing by two for the boundary average current. · Saying the inductor current goes negative in DCM instead of clamping at zero (true only for a synchronous buck operating in forced-CCM, not standard DCM).

6. 6You connect a board with about 2mF of total bulk capacitance to a bench supply. The moment you flip the supply on, its overcurrent protection trips, even though the board's steady-state current draw is well within the supply's rated current. Walk through what's happening and how you'd fix it, considering changes on both the supply side and the board side.medium

   The board works fine once actually running; the failure happens only at the instant of power-up.

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   Or just show what a strong answer covers

   At power-up, that 2mF of bulk capacitance is fully discharged, so the moment the supply applies voltage, it looks almost like a short circuit until the caps charge up — you get a very large instantaneous current spike, way above the board's steady-state draw. The bench supply's overcurrent protection is tripping on that peak, not on the real operating current. I'd confirm this with a current probe and scope capturing the very first milliseconds after turn-on. To fix it on the board side, I'd add inrush limiting — either a simple NTC thermistor in series with the input, or better, an active soft-start circuit using a series MOSFET whose gate is ramped up slowly by an RC network or a dedicated hot-swap controller, so the rail rises gradually and the caps charge over tens of milliseconds instead of instantly. On the supply side, I'd also check if the bench supply has an adjustable current limit or soft-start setting I could raise temporarily just to characterize the actual inrush profile.

   • Identifies inrush as the cause — States that charging the discharged bulk capacitance causes a large instantaneous current spike at power-up, unrelated to steady-state draw.
   • Explains why the trip happens despite fine steady-state numbers — Explains the overcurrent protection reacts to the peak/instantaneous current, which can be far higher than steady-state even briefly.
   • Proposes a board-side fix — Suggests a concrete mechanism like soft-start circuitry, NTC thermistor, or a hot-swap/inrush-limiting MOSFET controller that ramps the rail up over time.
   • Proposes a supply-side consideration — Mentions checking/adjusting the bench supply's current limit or soft-start/ramp setting, or measuring the actual inrush with a scope and current probe to size the fix.

   Where answers go wrong: Assuming the board itself is drawing too much steady-state current and looking for a short circuit instead of considering inrush. · Proposing to just raise the supply's current limit without addressing the underlying spike or board reliability. · Not mentioning any way to measure/verify the inrush magnitude before proposing a fix.

7. 7An LDO drops 12V to 5V while supplying 1A continuously. First, calculate the power it dissipates. Then, given a package thermal resistance junction-to-ambient of 50°C/W and an ambient of 45°C, reason about whether this is a workable design, and what you'd change if not.medium

   No heatsink is assumed unless you argue one is needed.

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   Or just show what a strong answer covers

   Power dissipated is (12-5)*1 = 7W. With an Rth-JA of 50°C/W and 45°C ambient, junction temperature would be 45 + 7*50 = 395°C — nowhere near feasible, since silicon junctions are typically rated around 125 to 150°C. So this design doesn't work as an LDO in this package with no heatsink; you'd need an enormous heatsink to bring the effective thermal resistance down by nearly an order of magnitude, which usually isn't practical for 7W in a small package. The real fix is to not use a linear regulator for this much drop and current at all — a switching buck converter would only dissipate a fraction of that power as heat, making the whole thermal problem go away rather than trying to manage it after the fact.

   • Correct power calculation — Computes P = (12-5)*1 = 7W.
   • Correct junction temperature estimate — Computes Tj = 45 + 7*50 = 395°C and recognizes this vastly exceeds any silicon's rated junction temperature (~125-150°C).
   • Concludes design is not viable as-is — States clearly that this configuration cannot work with this package/no heatsink and must be redesigned, not just 'add a bigger heatsink'.
   • Proposes a real fix — Recommends switching to a buck converter for this much voltage drop and current, since a heatsink alone couldn't realistically bring 7W down to a safe Rth via air cooling in this scenario, or at minimum flags that a drastically lower Rth package/heatsink is required.

   Where answers go wrong: Forgetting to multiply by current and just using the voltage difference as the answer. · Computing the junction temperature but not comparing it against a realistic maximum rating. · Suggesting 'add a heatsink' without recognizing how large a Rth reduction would actually be needed, or that a topology change is the more sensible fix.

8. 8You're wiring up a board where an FPGA needs its 1.8V core rail to come up only after its 3.3V I/O rail is stable, with a maximum allowed delay between the two per the datasheet. Walk me through how you'd implement that sequencing in hardware, and what could go wrong electrically if the rails come up in the wrong order or too far apart in time.medium

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   I'd use the first regulator's power-good output to drive the enable pin of the second regulator, or use a dedicated power sequencer/supervisor IC if there are more than two rails, rather than relying purely on an RC delay on the enable pin — a fixed delay doesn't guarantee the first rail is actually within spec by the time the second turns on, especially if load current or capacitor tolerance shifts the rise time. Electrically, if the 1.8V core comes up before or too far after the 3.3V I/O rail, current can flow through internal ESD or clamp diodes between the two domains, or in some processes trigger latch-up, potentially damaging the part or causing it to boot into an undefined state. To verify, I'd probe both rails simultaneously on a scope, trigger on the first rail crossing its regulation threshold, and measure the delay to the second rail crossing its own threshold, comparing that against the datasheet's max/min sequencing window across a few power cycles and load conditions.

   • Concrete implementation named — Describes at least one specific mechanism: power-good-to-enable chaining, a dedicated sequencer IC, or an RC delay on the enable pin.
   • Identifies the electrical risk — Names the actual failure mechanism: current flowing through internal ESD/clamp diodes between supply domains, or latch-up, when the order or delay is wrong.
   • Prefers feedback over open-loop timing — Notes that power-good/enable feedback is more robust than a fixed RC delay because rise time can vary with load or cap tolerance.
   • Describes bench verification — Explains how to confirm the sequencing works, e.g. probing both rails simultaneously on a scope and measuring the delay window against spec.

   Where answers go wrong: Assumes a fixed RC delay is always good enough regardless of load or capacitor tolerance. · Never explains the actual electrical failure mode, just says 'it could damage the chip'. · Doesn't mention verifying the sequencing with real measurements.

9. 9A buck-converter-powered board passes every test at room temperature on the bench, but in a hot enclosure at 55°C ambient, running continuously at full load, the downstream microcontroller resets sporadically. A quick scope check of the supply rail at room temperature looked clean. Walk through how you'd debug this thermally-dependent failure, and specifically what changes at elevated temperature that wouldn't have shown up in your room-temperature bench check.hard

   The failure only appears after the board has been running hot for a while, not immediately at power-up.

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   First I'd try to reproduce it in a controlled way — put the board in a thermal chamber at 55°C, run it at full load, and actually scope the rail and, if possible, the microcontroller's reset/brownout line while it's hot, rather than trusting a room-temperature snapshot. At elevated temperature, several things change that a quick room-temp check wouldn't show: the buck's MOSFETs have higher Rds(on), increasing conduction losses and self-heating, which can push efficiency down and increase output ripple; ceramic output capacitors lose a significant fraction of their effective capacitance under both temperature and DC bias, which weakens exactly the high-frequency filtering that's protecting the microcontroller from transient droop; and there can be small shifts in the regulator's reference voltage or UVLO threshold with temperature that move the trip point closer to the operating rail. There's also a self-reinforcing aspect — as losses rise, temperature rises further, which can compound these effects over the sustained run rather than showing up instantly. I'd want to isolate whether the droop is happening at the regulator's output or specifically at the microcontroller's own supply pin, since local decoupling near the MCU could also be under-provisioned once the ceramic caps derate. Only after seeing exactly where and when the droop or threshold crossing happens would I decide whether the fix is a different capacitor dielectric/rating, better local decoupling, or a regulator with more thermal margin.

   • Identifies temperature-dependent component behavior — Names at least two concrete mechanisms that change with temperature (e.g., MOSFET Rds(on) rise, ceramic cap capacitance derating, reference/tempco drift) rather than a generic 'things get worse when hot'.
   • Proposes an instrumented reproduction plan — Describes running the board in a thermal chamber while actively scoping the rail (and ideally the reset/UVLO pin) at load, rather than just re-testing at room temperature.
   • Distinguishes regulator-side vs load-side causes — Explicitly separates whether the fault is in the buck's output regulation/ripple versus the microcontroller's own local decoupling or brownout threshold being crossed.
   • Explains why room-temperature bench check missed it — Explains that the failure mode depends on cumulative self-heating and derated component values that simply aren't present at room temperature and short-duration testing.
   • Names a self-reinforcing thermal mechanism — Mentions that rising losses due to temperature can further raise temperature, describing a feedback effect rather than treating each factor in isolation.

   Where answers go wrong: Assuming the room-temperature scope trace being 'clean' rules out the power rail as a cause of a hot-only failure. · Jumping straight to 'it's the microcontroller's firmware' without first re-checking the supply under matched thermal and load conditions. · Naming only one temperature effect (e.g. just capacitor derating) instead of considering the several plausible mechanisms and how to distinguish them. · Not proposing to reproduce the fault with active monitoring in the chamber, instead relying only on post-mortem inspection.

10. 10You're bench-testing a buck converter board across a range of load currents. Efficiency looks reasonable at low-to-mid load, but as you push the load current higher, efficiency drops noticeably and you notice the inductor is hot to the touch while the FETs stay only warm. What's your hypothesis for what's dominating the loss, and how would you confirm it on the bench?hard

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    Since the FETs stay cool, switching losses — gate charge, dead-time conduction, reverse recovery — probably aren't the dominant mechanism, because those would show up as heat in the FETs, not the inductor. That points to the inductor itself: either straightforward I^2*DCR conduction loss, which scales with the square of load current and can become dominant well before you'd expect from a room-temperature datasheet number, or the inductor is approaching its saturation current rating, causing its effective inductance to drop, ripple current to increase nonlinearly, and core losses to spike. To confirm, I'd first measure the inductor's actual DCR with an ohmmeter or LCR bridge and calculate expected I^2R loss at the load current in question, comparing that against the measured temperature rise using the package's thermal resistance. Then I'd scope the actual inductor current waveform at high load looking for the ramp getting noticeably steeper or nonlinear near the peak, which is the telltale sign of falling inductance from saturation, and check that peak current against the part's rated saturation current. Depending on which one dominates, the fix is either a lower-DCR inductor or one with a higher saturation current rating for the same footprint.

    • Primary hypothesis: I^2*DCR conduction loss — Identifies quadratic scaling of inductor copper loss with load current as the leading suspect given the symptom.
    • Alternate hypothesis: core saturation — Raises the possibility that the inductor is approaching or exceeding its rated saturation current, degrading inductance and distorting the waveform.
    • Bench check for conduction loss — Proposes measuring the inductor's DCR (ohmmeter or LCR bridge) and calculating I^2R against the observed load current to see if it accounts for the temperature rise.
    • Bench check for saturation — Proposes scoping the inductor current waveform at high load to look for the ramp slope steepening or distortion characteristic of falling inductance near saturation.
    • Reasoning from FET temperature — Explicitly uses the fact that FETs are cool to rule out switching loss, gate drive loss, or reverse recovery as the dominant mechanism.

    Where answers go wrong: Jumps straight to blaming switching losses or gate drive without accounting for the FETs staying cool. · Doesn't propose any concrete measurement, just states a hypothesis. · Treats core saturation and DCR conduction loss as the same mechanism instead of two distinct, separately checkable hypotheses.